Datasheet4U Logo Datasheet4U.com

VIC068A-UMB - VMEbus Interface Controller

Download the VIC068A-UMB datasheet PDF. This datasheet also covers the VIC variant, as both devices belong to the same vmebus interface controller family and are provided as variant models within a single manufacturer datasheet.

General Description

The VMEbus interface controller (VIC068A) is a single chip designed to minimize the cost and board area requirements and to maximize performance of the VMEbus interface of a VMEbus master/slave module.

This can be implemented on VIC068A either an 8-bit, 16-bit, or 32-bit VMEbus system.

Key Features

  • Complete VMEbus interface controller and arbiter.
  • 58 internal registers provide configuration control and status of VMEbus and local operations.
  • Drives arbitration, interrupt, address modifier utility, strobe, address lines A07 through A01 and data lines D07 through D00 directly, and provides signals for control logic to drive remaining address and data lines.
  • Direct connection to 68xxx family and mappable to non-68xxx processors Complete master/slave capabil.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (VIC-068.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
VIC068 VMEbus Interface Controller VTC

Other Datasheets by Cypress (now Infineon)

Part Number Description
VIC068A-UM VMEbus Interface Controller
VIC068A-AC VMEbus Interface Controller
VIC068A-BC VMEbus Interface Controller
VIC068A-GC VMEbus Interface Controller
VIC068A-GI VMEbus Interface Controller

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
VIC068A VMEbus Interface Controller Features • Complete VMEbus interface controller and arbiter — 58 internal registers provide configuration control and status of VMEbus and local operations — Drives arbitration, interrupt, address modifier utility, strobe, address lines A07 through A01 and data lines D07 through D00 directly, and provides signals for control logic to drive remaining address and data lines — Direct connection to 68xxx family and mappable to non-68xxx processors Complete master/slave capability • — Supports read, write, write posting, and block transfers — Accommodates VMEbus timing requirements with internal digital delay line (1⁄ 2-clock granularity) — Programmable metastability delay — Programmable data acquisition delays — Provides timeout timers for local bus and VME